1. Technical Field
The present invention relates to integrated circuits and planars. In particular, the present invention relates to improved methods and systems for detecting defects within integrated circuits and planars. More particularly, the present invention relates to pseudo-random number generators utilized in testing integrated circuits and planars at the system level.
Still more particularly, the present invention relates to the automated testing of integrated circuits and planars for defects by using pseudo-random number generators and minimal supporting logic. The present invention also relates to a method and system for the isolation and testing of defects which manifest as data errors within integrated circuits and planars.
2. Description of the Related Art
As the integrated circuit art has advanced, more and more circuit devices, and consequently more and more circuit functions, have been placed on single chips. These developments have created problems in the testing of such chips. For example, while the testing of even an extremely large memory array chip may be relatively straightforward, a chip that integrates various types of functions, including an embedded memory array and logic, may pose problems for the circuit designer/tester who desires adequate testability of embedded structures. For example, embedded memory arrays typically possess far fewer input/output (I/O) pins available for the circuit tester than a memory array occupying a stand alone chip.
Control logic, such as arbitration, data routing, and bus interface unit logic, is also difficult to verify due to the increasing complexity of such units. As complexity has increased, the level of difficulty of error-free designs has also rapidly increased due to an increasing number of available scenarios (including timing windows), some of which may be overlooked by the designer. Verifying that the logic operates properly is thus more difficult due to the coverage problem (i.e., ensuring that all such timing windows have been exercised).
Complex planars (i.e., systems) also pose numerous verification problems. Not only must each pad and connector be verified (which is a relatively simple process, typically carried out by a bed-of-nails type of analyzer), but analog phenomena such as crosstalk and thermal problems must also be considered. Such analog phenomena and thermal problems may be very difficult to isolate.
When initially implementing new systems that possess integrated circuit components, the initial start up process may be riddled with difficulties due to defects present in the integrated circuits, memory units, planars, and other components within the system itself. Most defects at the system level can be detected as data corruption errors (i.e., returned data not matching expected data). Other types of errors/bugs fall into the livelock/deadlock category.
Depending upon the severity of the defects, debugging is largely a matter of tedious trial and error. The debugger utilized by the designer is essentially a program or programs that can be utilized to detect, trace, and eliminate errors in computer programs or other software. Automated data-checking schemes which provide sophisticated bit error detection/correction can be thrown off by multiple bit errors or even a single bit error in a checksum field, as well as scenarios where the data is parity-correct but still does not match expected data.
Thus, from the foregoing it can be appreciated that a need exists in the semiconductor art for testing structures and corresponding testing methods which allow for testing of multiple integrated circuit and planar structures.